Make

Makefiles are automation built around shellscripts,
they are normally used to codify build instructions, but can be used for anything.

Documentation

Gnu Makefile conventions	https://www.gnu.org/prep/standards/html_node/Makefile-Conventions.html
Text Function Reference (ex: ($shell ..) $(patsubst ..))	https://www.gnu.org/software/make/manual/html_node/Text-Functions.html
Automatic Variables (ex: $@, $<)	https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables

Tutorials

university of maryland tutorial	http://www.cs.umd.edu/class/fall2002/cmsc214/Tutorial/makefile.html
mrbook tutorial	http://mrbook.org/blog/tutorials/make/

Notes

make usage

make basics

make examples

Core Concepts

At it's core, a makefile is responsible for doing 3x things:

• configuring compiler to use, and compiler-flags
• defining program to compile, and all the object-files it is dependent on
• defining each object-file, it's cpp/header files, and all other dependent header files

makefile

Compiler

The makefile itself seems quite flexible with how you use it, but there seems to be an agreed-upon standard for what variables refer to what. Here are some of the more common variables:

PROG=		## name of output executable
OBJS=		## name of all *.o files to be included (?)

CC=		## compiler name
DEBUG=	## compiler flags for debug-mode (allow use of gdb)
CFLAGS=	## compiler flags for *.o object-file compilation
LFLAGS=	## compiler flags to determine libraries (?)

files/dependencies

The majority of your makefile defines files to be compiled, and their dependencies. You can define as many executables or *.o as you like, but by default only the first program (and all

• .o files it is dependent on) are compiled.

Movie.o: Movie.cpp Movie.h OtherModule.h
	g++ -Wall -c Movie.cpp

Other

make builtins

gnu-make has a subset of commands that you can use within your makefile.

See excellent documentation: https://www.gnu.org/software/make/manual/html_node/Text-Functions.html .

@command              # run cli-command
$(shell  command)     # assign output of cli-command to var

$(subst from,to,text)
$(patsubst %.c,%.o,file1.c file2.c file3.c)  # '%' is a wildcard match. '%'s value is preserved in replacement
$(var:pattern=replacement)                   # single variable pattern-replacement

create directory

Occasionally, it makes sense to specify the creation of directories in your makefile. (such as creating a /bin directory that can be put in .gitignore). You can do this with the following snippet:

BINDIR = bin
   dummy_build_folder := $(shell mkdir -p $(BINDIR))

echo variable

Sometimes it's handy to try to figure out just what exactly your compiler is running. You can do this. using a prefix of @ runs a shell command.

all:
	@clear
	@echo "_INCL:   $(_INCL)"
	@echo "_SRCDIR: $(_SRCDIR)"

Sources

http://www.cs.umd.edu/class/fall2002/cmsc214/Tutorial/makefile.html

http://mrbook.org/blog/tutorials/make/